BCA PAPER CODE BCAC201 SEM -2 [2024]

 

MAULANA ABUL KALAM AZAD UNIVERSITY OF TECHNOLOGY, WEST BENGAL

Paper Code: BCAC201
Computer Architecture
UPID: 2000077

Time Allotted: 3 Hours
Full Marks: 70

The figures in the margin indicate full marks.
Candidates are required to give their answers in their own words as far as practicable.

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Group-A (Very Short Answer Type Questions)

Answer any ten of the following: (1 × 10 = 10)

1. Convert 41.6875 in decimal to its equivalent binary.

2. Booth’s algorithm gives a procedure for multiplying binary integers in ______ complement representation.

3. The time taken for a disk drive to locate the area on the disk where the data is stored is called ______.

4. The expression AB + CD in reverse Polish notation is ______.

5. Represent 248 in decimal to its equivalent BCD code.

6. SIMD stands for ______.

7. The arithmetic micro-operation R3 ← R1 + R2' + 1 means ______.

8. The register symbol IR identifies ______ register.

9. A memory that is part of a control unit is referred to as ______ memory.

10. If the stack is not full (FULL = 0), a new item is inserted with a ______ operation.

11. In pipeline processing, a task is defined as the total operation performed going through all segments in the ______.

12. The ______ pulse method and the handshaking method are used for asynchronous data transfer between independent units.

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Group-B (Short Answer Type Questions)

Answer any three of the following: (5 × 3 = 15)

2. Signed Magnitude Addition/Subtraction

• Draw the flowchart and hardware diagram for signed magnitude addition and subtraction.

3. Register Transfer & Asynchronous Data Transfer

• Explain register transfer and control functions.

• Discuss strobe and handshaking methods for asynchronous data transfer.

4. Input-Output Instructions

• Discuss any 5 I/O instructions (e.g., IN, OUT, LOAD, STORE, SKIP).

5. Flynn’s Classification

• Classify computers based on parallel processing (SISD, SIMD, MISD, MIMD).

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Group-C (Long Answer Type Questions)

Answer any three of the following: (15 × 3 = 45)

7. Types of Interrupts

• Hardware interrupts (e.g., I/O, timer).

• Software interrupts (e.g., system calls).

• Maskable vs. non-maskable interrupts.

8. Floating-Point Pipeline Unit

• Design a pipeline unit for floating-point addition/subtraction.

• Example: Add 1.5 × 10³ + 2.5 × 10² with pipeline stages (alignment, addition, normalization).

9. Binary Arithmetic Operations

• a. Perform:

  • (i) 0011010 + 001100

  • (ii) 0011010 – 001100

• b. Multiply: 0011010 × 001100

• c. Divide: 101010 / 000110

10. Cache Memory Organization

• a. Associative mapping: Fully flexible placement.

• b. Direct mapping: Fixed cache location per block.

• c. Set-associative mapping: Hybrid (blocks mapped to sets).

11. Address Sequencing in Microprogrammed Control

• Microinstruction sequencing (sequential, branch, subroutine calls).

• Mapping (next-address generator, control memory).

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Solutions

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Group-A (Very Short Answer Type Questions)

Solutions (Any 10):

1. Decimal to Binary (41.6875):

   • Integer part (41): 101001

   • Fractional part (0.6875): 0.1011

   • Final answer: 101001.1011

2. Booth’s Algorithm: Uses 2’s complement representation for signed binary multiplication.

3. Disk Access Time: Seek time (time to position the disk head).

4. Reverse Polish Notation (AB + CD): A B * C D * +

5. Decimal to BCD (248):

   • 2 → 0010, 4 → 0100, 8 → 1000

   • Final answer: 0010 0100 1000

6. SIMD: Single Instruction, Multiple Data (e.g., vector processors).

7. Micro-operation (R3 ← R1 + R2' + 1):

   • Subtracts R2 from R1 (since R2' + 1 is the 2’s complement of R2).

8. IR Register: Instruction Register (holds the current instruction).

9. Control Unit Memory: Control Memory (Microprogram Memory).

10. Stack Insert Operation: PUSH (when FULL = 0).

11. Pipeline Task: Pipeline segment (all stages must complete for one task).

12. Asynchronous Data Transfer Methods:

    • Strobe pulse (single control line).

    • Handshaking (two-way synchronization).

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Group-B (Short Answer Type Questions)

2. Signed Magnitude Addition/Subtraction

Flowchart & Hardware:

• Steps:

  1. Compare signs of operands.

  2. If same, add magnitudes; else, subtract smaller from larger.

  3. Assign the sign of the larger operand.

• Hardware: Requires comparator, adder/subtractor, and sign logic.

3. Register Transfer & Asynchronous Data Transfer

Register Transfer:

• Notation: R1 ← R2 + R3 (data moved via control signals).

Asynchronous Transfer Methods:

• Strobe: Single pulse from sender to receiver.

• Handshaking: Uses READY (sender) and ACK (receiver) signals.

4. Input-Output Instructions

Examples:

1. IN (Read from I/O port).

2. OUT (Write to I/O port).

3. LOAD (Move data to CPU register).

4. STORE (Save data to memory).

5. SKIP (Conditional I/O operation).

5. Flynn’s Classification

Categories:

1. SISD (Single Instruction, Single Data): Traditional CPU.

2. SIMD (Single Instruction, Multiple Data): GPUs.

3. MISD (Multiple Instruction, Single Data): Rare (e.g., fault-tolerant systems).

4. MIMD (Multiple Instruction, Multiple Data): Multi-core processors.

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Group-C (Long Answer Type Questions)

7. Types of Interrupts

1. Hardware Interrupts:

• Maskable: Can be delayed (e.g., I/O interrupts).

• Non-maskable: Critical (e.g., power failure).

2. Software Interrupts:

• Trap: User-initiated (e.g., system calls).

• Exception: Error-induced (e.g., division by zero).

Example:

• I/O Interrupt: Printer finishes printing.

8. Floating-Point Pipeline

Stages:

1. Alignment: Match exponents.

2. Addition/Subtraction: Perform operation.

3. Normalization: Adjust mantissa.

Example:

• 1.5 × 10³ + 2.5 × 10² → Align exponents (2.5 × 10² → 0.25 × 10³).

• Add: 1.5 + 0.25 = 1.75 × 10³.

9. Binary Arithmetic

a. Addition (0011010 + 001100):

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  0011010 (26)  
+  001100 (12)  
------------  
  0100110 (38)  

b. Multiplication (0011010 × 001100):

• Use shift-add: 26 × 12 = 312 (100111000 in binary).

c. Division (101010 / 000110):

• 42 / 6 = 7 (000111 in binary).

10. Cache Mapping Techniques

a. Associative Mapping:

• Any block can go anywhere in cache (fully flexible).

b. Direct Mapping:

• Each block maps to one fixed cache line (e.g., Block N → Cache line (N mod C)).

c. Set-Associative Mapping:

• Blocks map to sets (each set has k lines).

11. Address Sequencing

Steps:

1. Fetch: Read microinstruction from control memory.

2. Execute: Perform micro-operation.

3. Next Address: Determined by:

   • Sequential counter.

   • Branch conditions.

Example:

• If (Condition) then Branch else PC + 1.

Thanks

SK Institute